Front side bus

From Academic Kids

Front Side Bus (FSB) is the term used to describe the CPU data bus. This bus carries all information that passes from the CPU to other devices within the system such as RAM, PCI expansion cards, hard disks, etc.

Some computers have an L2 or L3 cache external to the CPU connected via a back side bus. This bus and the cache memory connected to it is faster than accessing the system RAM via the front side bus.

Contents

Current usage

Most modern buses (both GTL+ and EV6) serve as a backbone between the CPU and a chipset. This chipset (usually a combination of northbridge and southbridge) is the connection point for all other buses in the system. The PCI, AGP, and Memory buses all connect to the chipset to allow for data to flow between the connected devices.

These secondary system buses usually run at speeds derived from the front side bus' speed. In general, a faster front side bus means higher processing speeds and a faster computer for a number of reasons which are outlined below.

Overclocking and related bus speeds

CPU

The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front side bus (FSB) speed. For example, a processor running at 550 MHz might be using a 100 MHz FSB. This means there is an internal clock multiplier setting of 5.5; the CPU is set to run at 5.5 times frequency of the front side bus: 100 MHz x 5.5 = 550 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved.

Most motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings. Many CPU manufacturers now "lock" a preset multiplier setting into the chip, which causes the manually-set multiplier settings to be ignored in favour of the locked-in multiplier. It is possible to unlock some locked CPUs. For instance, some Athlons can be unlocked by connecting electrical contacts across points on the CPU's surface. For all processors, the FSB speed can be increased to boost processing speed (called overclocking).

Memory

Setting a FSB speed is related directly to the speed grade of memory that a system must use. The memory bus connects the northbridge and RAM, just as the frontside bus connects the CPU and northbridge. Often, these two buses must operate at the same frequency. Pushing the front-side bus to 170 MHz means pushing the memory to 170 MHz in most cases.

Similar to the PCI and AGP buses, however, the memory bus can sometimes also be run asynchronously from the front side bus. In Pentium 4 systems, it is possible to see memory ratios of "5:4" and the like. The bus will run 5/4 faster than the memory in this situation, meaning a 200 MHz bus can run with the memory at only 160 MHz. With bus speeds increasing rapidly, it is sometimes necessary to run the RAM at a lower frequency than the system bus in order to stay within the limitations of the DRAM modules on the memory stick. This incurs a performance penalty, but it allows slower RAM to be used with the faster bus speeds that some processors were designed for.

In complex image, audio, video, and scientific applications where the data set is large, FSB speed becomes a major performance issue. A slow FSB will cause the CPU to spend significant amounts of time waiting for data to arrive from system memory.

Some sample FSB frequencies and bandwidths

Processor ClassFSB FrequencyTheoretical Bandwidth
Pentium II66/100 MHz533/800 MB/s
Pentium III100/133 MHz800/1066 MB/s
Pentium IV*100/133/200/266 MHz3200/4200/6400/8533 MB/s
Athlon**100/133 MHz1600/2100 MB/s
Athlon XP**133/166/200 MHz2100/2700/3200 MB/s
Athlon 64/FX/Opteron***600/800/1000 MHz4800/6400/8000 MB/s
PowerPC 970900/1000/1250 MHz7200/8000/10000 MB/s
Notes:
* - Pentium IV processors use a frontside bus that transfers data four times per cycle
** - Athlon and Athlon XP processors use a frontside bus that transfers data twice per cycle
*** - Athlon 64, FX, and Opteron processors have a memory controller on the CPU die, which replaces the traditional FSB, the clockspeed and bandwidth given here is for the HyperTransport link between the CPU and northbridge

History

The frontside bus has been a part of computer architecture since applications first started using more memory than a CPU (a very complex integrated circuit) could reasonably hold.

The front side bus as it is traditionally known may be disappearing. Originally, this bus was a central connecting point for all system devices and the CPU. However, in recent years this has been breaking down with the use of more and more individual point-to-point buses.

Three recent bus technologies are GTL+, EV6, and HyperTransport. Each bus is unique in how it moves data within the system between the CPU and devices.

GTL+/AGTL+

  • Designed by Intel for the Pentium Pro, Pentium II, and Pentium III CPUs, as well as Xeons based on these cores (GTL+)
  • Redesigned for the Pentium 4 as well as Xeons on the same cores (AGTL+)
  • A "shared" bus, meaning that all CPUs compete over the same physical connection for the bus' bandwidth.

EV6 Bus

  • Designed by DEC (now part of HP) for use with their Alpha EV6 CPUs
  • Licensed by AMD for their Athlon and Athlon XP line of CPUs
  • A point-to-point protocol connecting each CPU to the northbridge, meaning that each CPU has a dedicated connection to the device.

HyperTransport

  • A point-to-point bus used by AMD for their Athlon64, AthlonFX, and Opteron lines of CPUs.
  • Not technically a front side bus. The HyperTransport bus is used to connect parts of the system together. This is listed because it is the only bus that allows communication between the processor and the rest of the system, which was traditionally one of the functions of the frontside bus. On AMD-64 CPUs, the frontside bus, which connected the CPU to the northbridge, has been removed in favor of an on-die memory controller.

External links

pl:Front side bus

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